HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 490

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HD64F2168VTE33

Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F2168VTE33

Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

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Bit
2
0
Rev. 3.00, 03/04, page 448 of 830
Bit Name
BBSY
SCP
Initial
Value
0
1
R/W
R/W*
W
3
Description
Bus Busy
Start Condition/Stop Condition Prohibit
In master mode
In slave mode
[BBSY setting condition]
[BBSY clearing conditions]
To issue a start/stop condition, use the MOV instruction.
The I
before the issue of a start condition. Set MST to 1 and
TRS to 1 before writing 1 in BBSY and 0 in SCP.
The BBSY flag can be read to check whether the I
(SCL, SDA) is busy or free.
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
Writing 1 in BBSY and 0 in SCP: A start condition and
a restart condition are issued
Writing to the BBSY flag is disabled.
When the SDA level changes from high to low under
the condition of SCL = high, assuming that the start
condition has been issued.
When the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued.
2
C bus interface must be set in master transmit mode
2
C bus

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