HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 524

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Continuous Receive Operation:
Figure 15.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Rev. 3.00, 03/04, page 482 of 830
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
Read AASX, AAS and ADZ in ICSR
No
No
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Set ACKB = 1 in ICSR
Slave receive mode
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read TRS in ICCR
Wait for one frame
and ADZ = 1?
Set MST = 0
(n-2)th-byte
ICDRF = 1?
ESTP = 1 or
ICDRF = 1?
ICDRF = 1?
Read ICDR
Read ICDR
STOP = 1?
Read ICDR
reception?
IRIC = 1?
TRS = 1?
IRIC = 1?
AAS = 1
End
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
No
No
Yes
* n: Address + total number of bytes received
Slave transmit mode
[3] to [7] Wait for one byte to be received (slave address + R/W)
[11] Wait for one byte to be received
[1] Select slave receive mode.
General call address processing
[9] Wait for ACKB setting and set acknowledge data
[10] Read the receive data. The first read is a dummy read.
[12] Detect stop condition
[2] Read the receive data remaining unread.
[8] Clear IRIC
[13] Clear IRIC
[14] Read the last receive data
[15] Clear IRIC
(after the rise of the 9th clock of (n-1)th byte data)
for the last reception
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the rise of the 9th clock)
* Description omitted