HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 563

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.3.3
HICR4 controls the selection of access channel when setting addresses for LPC channels 1 and 2,
and the operation of KCS, SMIC, and BT interfaces included in channel 3.
Bit
7
6 to 4 
3
2
1
0
Bit Name
LADR12SEL 0
SWENBL
KCSENBL
SMICENBL
BTENBL
Host Interface Control Register 4 (HICR4)
Initial Value Slave Host Description
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W






Switches the access channel of LADR12H,
LAD12L.
0: LADR1 is selected
1: LADR2 is selected
Reserved
The initial value should not be changed.
In BT mode, H'5 (short wait) or H'6 (long wait) is
returned to the host in the synchronized return
cycle from slave, thus can make the host wait.
0: Short wait is issued
1: Long wait is issued
Enables or disables the use of the KCS interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: KCS interface operation is disabled
1: KCS interface operation is enabled
Enables or disables the use of the SMIC interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: SMIC interface operation is disabled
1: SMIC interface operation is enabled
Enables or disables the use of the BT interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: BT interface operation is disabled
1: BT interface operation is enabled
No address (LADR3) matches for IDR3, ODR3,
or STR3 in KCS mode
No address (LADR3) matches for SMICFLG,
SSMICCSR, or SMICDTR
No address (LADR3) matches for BTIMSR,
BTCR, or BTDTR
Rev. 3.00, 03/04, page 521 of 830