HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 714

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

(2)
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 20.20.
(3)
After adjustment of the bit rate, the protocol for communications between the host and the boot
program is as shown below.
1. 1-byte commands and 1-byte responses
2. n-byte commands or n-byte responses
3. Error response
4. Programming of 128 bytes
5. Memory read response
Rev. 3.00, 03/04, page 672 of 830
These commands and responses are comprised of a single byte. These are consists of the
inquiries and the ACK for successful completion.
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The amount of programming data is not included under this heading because it is determined
in another command.
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
The size is not specified in commands. The size of n is indicated in response to the
programming unit inquiry.
Bit-Rate-Adjustment State
Communications Protocol
Host
Figure 20.20 Bit-Rate-Adjustment Sequence
H'00 (Completion of adjustment)
H'E6 (Boot response)
H'00 (30 times maximum)
(H'FF (error))
H'55
Boot Program
Measuring the
1-bit length