HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 591

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Bit
7 to 5 
4
3
2
Bit Name Initial Value Slave Host Description
HDTWI
HDTRI
STARI
All 0
0
0
0
R/W
R/(W)* 
R/(W)* 
R/(W)* 
R/W

Reserved
The initial value should not be changed.
Transfer Data Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the transfer data to SMICDTR.
When the IBFIE3 bit and HDTWIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data transmission wait state
[Clearing condition]
After the slave reads HDTWI = 1, writes 0 to this bit.
1: Transfer data transmission end
[Setting condition]
The transfer cycle is write transfer and the host
writes the transfer data to SMICDTR.
Transfer Data Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the transfer data from SMICDTR.
When the IBFIE3 bit and HDTRIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data receive wait state
[Clearing condition]
After the slave reads HDTRI = 1, writes 0 to this bit.
1: Transfer data receive end
[Setting condition]
The transfer cycle is read transfer and the host
reads the transfer data from SMICDTR.
Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
Rev. 3.00, 03/04, page 549 of 830