HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 564

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.3.4
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
• LADR3L
Rev. 3.00, 03/04, page 522 of 830
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value Slave Host
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name Initial Value Slave Host
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3

Bit 1
TWRE
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
All 0
All 0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W





Description
Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
Description
Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
Reserved
The initial value should not be changed.
Channel 3 Address Bit 1
The host address of LPC channel 3 is set.
Bidirectional data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
1: TWR operation is enabled
TWR-related address (LADR3) match does not
occur.