HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 481

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

15.3
The I
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. The IIC registers are allocated to the same address.
Selecting register is carried out by means of the IICE bit in the serial timer control register
(STCR).
• I
• Slave address register (SAR)
• Second slave address register (SARX)
• I
• I
• I
• I
• I
• I
15.3.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in accordance with changes in the bus state, and they
affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If IIC is in transmit mode (TRS=1) and the next data is in ICDRT (the ICDRE flag is 0), data is
transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If IIC is in receive mode
(TRS=0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
2
2
2
2
2
2
2
C bus data register (ICDR)
C bus mode register (ICMR)
C bus transfer rate select register (IICX3)
C bus control register (ICCR)
C bus status register (ICSR)
C bus extended control register (ICXR)
C SMbus control register (ICSMBCR)
2
C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
Register Descriptions
I
2
C Bus Data Register (ICDR)
2
C bus format, writing transmit data to ICDR should be
Rev. 3.00, 03/04, page 439 of 830