HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 212

no-image

HD64F2168VTE33

Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F2168VTE33

Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2168VTE33
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F2168VTE33V
Manufacturer:
Renesas
Quantity:
8 400
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS
Quantity:
112
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
7.6.5
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and priority level control by the interrupt controller.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.6.6
Rev. 3.00, 03/04, page 170 of 830
φ
DTC activation
request
DTC request
Address
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Interrupt Sources
Operation Timing
Vector read
Transfer information
read
Data transfer
Read Write
Transfer information
write

Related parts for HD64F2168VTE33