HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 491

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Bit
1
Bit Name
IRIC
Initial
Value
0
R/W
R/(W)*
1
Description
I
Indicates that the I
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR and the WAIT bit in ICMR. See section 15.4.7, IRIC
Setting Timing and SCL Control. The conditions under
which IRIC is set also differ depending on the setting of the
ACKE bit in ICCR.
[Setting conditions]
I
•
•
•
•
•
•
I
•
•
•
•
2
2
2
C Bus Interface Interrupt Request Flag
C bus format master mode:
C bus format slave mode:
When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
At the end of data transfer (rise of the 9th
transmit/receive clock)
When a slave address is received after bus mastership
is lost
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
When the AL flag is set to 1 after bus mastership is lost
while the ALIE bit is 1
When the slave address (SVA or SVAX) matches (when
the AAS or AASX flag in ICSR is set to 1) and at the
end of data transfer up to the subsequent
retransmission start condition or stop condition detection
(rise of the 9th clock)
When the general call address is detected (when the 0
is received for R/W bit, and ADZ flag in ICSR is set to 1)
and at the end of data reception up to the subsequent
retransmission start condition or stop condition detection
(rise of the 9th receive clock)
When 1 is received as an acknowledge bit while the
ACKE bit is 1 (when the ACKB bit is set to 1)
When a stop condition is detected while the STOPIM bit
is 0 (when the STOP or ESTP flag in ICSR is set to 1)
2
C bus interface has issued an interrupt
Rev. 3.00, 03/04, page 449 of 830