HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 503

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Bit
4
Bit Name
ICDRE
Initial
Value
0
R/W
R
Description
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to ICDR
1: Indicates that data has been transferred from ICDRT to
[Setting conditions]
•
•
[Clearing conditions]
•
•
•
Note that if the ACKE bit is set to 1 in I
enabling acknowledge bit decision, ICDRE is not set when
data is transmitted completely while the acknowledge bit is
1.
When ICDRE is set due to the condition (2) above, ICDRE
is temporarily cleared to 0 when data is written to ICDR
(ICDRT); however, since data is transferred from ICDRT to
ICDRS immediately, ICDRF is set to 1 again. Do not write
data to ICDR when TRS = 0 because the ICDRE flag
value is invalid during the time.
(ICDRT) or ICDR is initialized.
ICDRS and is being transmitted, or the start condition
has been detected or transmission has been complete,
thus allowing the next data to be written to.
When the start condition is detected from the bus line
state in I
When data is transferred from ICDRT to ICDRS.
1. When data is transmitted completely while ICDRE
2. When data is written to ICDR completely in transmit
When data is written to ICDR (ICDRT).
When the stop condition is detected in I
or serial format.
When 0 is written to the ICE bit.
= 0 (at the rise of the 9th clock pulse).
mode after data was transmitted while ICDRE = 1.
2
C bus format or serial format.
Rev. 3.00, 03/04, page 461 of 830
2
C bus format thus
2
C bus format