HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 549

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. The LPC
interface operates as a slave and supports only I/O read cycle and I/O write cycle transfer.
It is also provided with power-down functions that can control the PCI clock and shut down the
LPC interface.
16.1
• Supports LPC interface I/O read cycles and I/O write cycles
• Has three register sets comprising data and status registers
• Supports SERIRQ
• Power-down functions, interrupts, etc.
• Supports version 1.5 of the Intelligent Platform Management Interface (IPMI)
IFHSTL1A_010020030700
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
Channels 1 to 3 have fixed I/O addresses of H'0000 to H'FFFF, respectively.
A fast A20 gate function is also provided.
Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set.
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
Channel 3 supports the SMIC interface, KCS interface, and BT interface.
Features
Section 16 LPC Interface (LPC)
Rev. 3.00, 03/04, page 507 of 830