HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 146

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

6.2
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Rev. 3.00, 03/04, page 104 of 830
Symbol
AS
IOS
CPCS1
CS256
RD
HWR
LWR
WAIT
AH
AD15 to AD0
Input/Output Pins
Pin Configuration
Output
Output
Output
Output
Output
Output
Output
Input
Output
I/O
Input/Output
Function
Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-kbyte
extended area is accessed (the CS256E bit in SYSCR is 1)
or when the CP extended area is accessed (the CPCSE bit
in BCR2 is 1).
Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
Chip select signal indicating that the CP extended area is
being accessed (when the CPCSE bit in BCR2 is 1).
Chip select signal indicating that the 256-kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
Strobe signal indicating that the external address space is
being read.
Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is enabled.
Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is enabled.
Wait request signal when accessing the external space.
Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
Address output and data input/output pins for address-data
multiplex extension.