HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 148

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HD64F2168VTE33

Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F2168VTE33

Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

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6.3.2
BCR2 is used to specify the access mode for the CP extended area.
Rev. 3.00, 03/04, page 106 of 830
Bit
3
2
1
0
Bit
7, 6
5
4
Bit Name
BRSTS0
IOS1
IOS0
Bit Name
ABWCP
ASTCP
Bus Control Register 2 (BCR2)
Initial
Value
0
0
1
1
Initial
Value
All 0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Valid only in the normal extended mode.
Burst Cycle Select 0
Selects the number of words that can be accessed by burst
access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
Reserved
The initial value should not be changed.
IOS Select 1 and 0
Select the address range where the IOS signal is output.
See table 6.15.
CP Extended Area Bus Width Control
CP Extended Area Access State Control
Description
Reserved
The initial value should not be changed.
Selects the bus width for access to the CP extended area
when the CPCSE bit is set to 1
0: 16-bit bus
1: 8-bit bus
Selects the number of states for access to the CP extended
area when the CPCSE bit is set to 1. This bit also enables or
disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled

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