HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 201

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

7.3
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below.
Table 7.2
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the
ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag
state, status/address codes are generated.
An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the
same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced
with address code that is generated by the ECS flag status.
Register
MRA
MRB
SAR
DAR
CRAH
CRAL
CRBH
CRBL
DTCERC
KBCOMP
RAM
DTC Event Counter
7, 6
5, 4
3, 2
1
0
7
6
5 to 0
23 to 0
23 to 0
7 to 0
7 to 0
7 to 0
7 to 0
4
7

Bit
DTC Event Counter Conditions
Bit Name
SM1, SM0 00: SAR is fixed.
DM1, DM0 00: DAR is fixed.
MD1, MD0 01: Repeat mode
DTS
Sz
CHNE
DISEL







DTCEC4
EVENTE

Description
0: Destination is repeat area
1: Word size transfer
0: Chain transfer is disabled
0: Interrupt request is generated when data is transferred by
B'000000
Identical optional RAM address. Its lower five bits are B'00000.
The start address of 16 words is this address. They are
incremented every time an event is detected in EVENT0 to
EVENT15.
H'FF
H'FF
H'FF
H'FF
1: DTC function of the event counter is enabled
1: Event counter enable
(SAR, DAR) : Result of EVENT0 count
(SAR, DAR) + 2: Result of EVENT 1 count
(SAR, DAR) + 4: Result of EVENT 2 count
(SAR, DAR) + 30: Result of EVENT 15 count
the number of specified times
↓
Rev. 3.00, 03/04, page 159 of 830