HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 447

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

14.6.5
Figure 14.23 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits
to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive
mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking
that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0,
simultaneously set the TE and RE bits to 1 with a single instruction.
14.6.6
SCI_0 and SCI_2 provide the following capability according to the serial enhanced mode registers
(SEMR_0 and SEMR_2) settings.
If the SCI is used in clock synchronous mode with clock input, the SCI channel can be
enabled/disabled using the input at the external pins. The external pins include PA0/SSE0I
(SCI_0) and PA1/SSE2I (SCI_2); therefore, this capability is not available in modes where the
PA0 and PA1 pins are automatically set for address output.
When the SCI operation is disabled (not selected) by input at the external pins, TxD output is
fixed to the high-impedance state and SCK input is internally fixed to high. One-to-multipoint
communication is possible if the master device, which outputs SCK, controls these external pins
for chip selection. SCI selection capability is selected using the SSE bits in SEMR.
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
SCI Selection in Serial Enhanced Mode
Rev. 3.00, 03/04, page 405 of 830