HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 575

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Bit
4
3
2
1
SWMF
C/D3
DBU32
IBF3A
Bit Name Initial Value Slave Host Description
0
0
0
0
R/(W)* R
R
R/W
R
R/W
R
R
R
Slave Write Mode Flag
Indicates that slave write mode is entered by writing
to TWR0 from the slave processor (this LSI). In the
event of simultaneous writes by the master and the
slave, the master write has priority.
0: [Clearing condition]
1: [Setting condition]
Command/Data
When the host processor writes to an IDR3 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR3 contains data or a command.
0: Content of input data register (IDR3) is data
1: Content of input data register (IDR3) is a
Defined by User
The user can use this bit as necessary.
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave processor reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host processor writes to IDR3 using I/O
write cycle
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
command
When the slave processor writes to TWR0 while
MWMF = 0
Rev. 3.00, 03/04, page 533 of 830