PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 98

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.32
7.5.33
7.5.34
PERICOM SEMICONDUCTOR - Confidential
SECONDARY LATENCY TIMER REGISTER – OFFSET 4Ch
SECONDARY HEADER TYPE REGISTER – OFFSET 4C
SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 50h
Bit
7:6
Bit
15:8
Bit
22:16
23
31:24
Bit
0
2:1
3
11:4
31:12
Function
Reserved
Function
Secondary Latency
Timer
Function
Other Bridge
Configuration
Single Function
Device
Reserved
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
Type
Type
Type
Type
RO / RW
RW/RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 98 of 165
Description
Bit [7:6] not supported
Reset to 00
Description
8 bits of secondary latency timer in PCI/PCI-X
REVERSE BRIDGE –
RO with reset to 00h
FORWARD BRIDGE –
RW with reset to 00h in PCI mode or 40h in PCI-X mode
Description
Type-0 header format configuration (10 – 3Fh)
Reset to 0000000
0: Indicates single function device
Reset to 0
Reset to 00h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Upstream
Memory 0 Setup Register (Offset E4h), which can be initialized by EEPROM
(I2C) or SM Bus or Local Processor. The range of this register is from 4KB
to 2GB. The lower 4KB if this address reange map to the PI7C9X130 CSRs
into memory space. The remaining space is this range above 4KB, if any,
specifies a range for forwarding upstream memory transactions.
PI7X9X110A uses upstream Memory 0 Translated Base Register (Offset E0h)
to formulate direct address translation. If a bit in the setup register is set to
one, then the correspondent bit of this register will be changed to RW.
Reset to 00000h
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130