PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 100

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.38
7.5.39
PERICOM SEMICONDUCTOR - Confidential
UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h
UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 64h
Bit
31:14
Bit
0
2:1
3
11:4
31:12
Bit
31:0
Function
Base Address
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
Function
Base address
Type
Type
Type
RW/RO
RW/RO
RO/RW
RO
RO
RO
RO
Page 100 of 165
Description
This Base Address register defines the address range for upstream memory
transactions. PI7C9X130 uses a lookup table to do the address translation.
The address range of this register is from 16KB to 2GB in memory space.
The address range is divided into 64 pages. The size of each page is defined
by Memory Address Forwarding Control register (Offset 6Ah), which is
initialized by EEPROM (I2C) or SM Bus or local processor. Writing a zero to
the bit [0] of the look up table entry can disable the corresponding page of this
register (CSR Offset 1FFh: 100h).
The number of writeable bit may change depending on the page size setup.
Reset to 00000h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Upstream
Memory 3 Setup Register (CSR Offset 034h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup registers (CSR Offset 034h and 038h) to disable this register. The
range of this register is from 4KB to 9EB for memory space.
uses this register and the Upstream Memory 3 Upper Base Address Register
when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit
addressing is disabled, no address translation is performed. All 64-bit address
transactions on the secondary interface falling outside of the Downstream
Memory 3 address range are forwarded upstream.
Reset to 00000h
Description
The size of this Base Address Register is defined from Upstream Memory 3
Upper 32-bit Setup Register (CSR Offset 038h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup registers (CSR Offset 038h) to disable this register. This register
defines the upper 32 bits of a memory range for upstream forwarding memory.
PI7C9X130 uses this register and the Upstream Memory 3 Base Address
Register when 64-bit addressing programmed (bit [21] of Offset 68h). When
64-bit addressing is disabled, no address translation is performed. All 64-bit
address transactions on the secondary interface falling outside of the
Downstream Memory 3 address range are forwarded upstream.
Reset to 00000000h
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130
PI7C9X130