PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 11

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
7.6
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CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE .....................134
RESERVED REGISTERS – OFFSET 000h TO 004h ........................................................................134
DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER – OFFSET 008h...........................134
DOWNSTREAM MEMORY 2 SETUP REGISTER – OFFSET 00Ch ................................................134
DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER – OFFSET 010h...........................135
DOWNSTREAM MEMORY 3 SETUP REGISTER – OFFSET 014h .................................................135
DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 018h .......................135
RESERVED REGISTERS – OFFSET 01Ch TO 030h........................................................................135
UPSTREAM MEMORY 3 SETUP REGISTER – OFFSET 034h .......................................................136
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 038h..............................136
RESERVED REGISTERS – OFFSET 3Ch TO 4Ch ...........................................................................136
LOOKUP TABLE OFFSET – OFFSET 50h ......................................................................................136
LOOKUP TABLE DATA – OFFSET 054h ........................................................................................137
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h............................137
UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER - OFFSET 05Ch ...........................138
UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER - OFFSET 060h...................................138
UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER - OFFSET 064h...................................138
RESERVED REGISTER – OFFSET 068C.........................................................................................138
MESSAGE DATA REGISTER – OFFSET FCh .............................................................................124
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .......................124
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h ...........124
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h .........................................................125
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ............................................125
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...............................................125
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch........................................126
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h..................................................126
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h.....................................................126
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h.................127
HEADER LOG REGISTER 1 – OFFSET 11Ch.............................................................................127
HEADER LOG REGISTER 2 – OFFSET 120h..............................................................................127
HEADER LOG REGISTER 3 – OFFSET 124h..............................................................................127
HEADER LOG REGISTER 4 – OFFSET 128h..............................................................................127
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch....................128
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h........................128
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h.................129
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h ..................130
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h ............................................130
RESERVED REGISTER – OFFSET 14Ch.....................................................................................130
VC CAPABILITY ID REGISTER – OFFSET 150h ........................................................................130
VC CAPABILITY VERSION REGISTER – OFFSET 150h ............................................................130
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h .........................................................130
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...............................................................131
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...............................................................131
PORT VC CONTROL REGISTER – OFFSET 15Ch .....................................................................131
PORT VC STATUS REGISTER – OFFSET 15Ch..........................................................................131
VC0 RESOURCE CAPBILITY REGISTER – OFFSET 160h.........................................................131
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ..........................................................132
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..............................................................132
RESERVED REGISTERS – OFFSET 16Ch TO 2FCh...................................................................132
EXTENDED GPIO DATA AND CONTROL REGISTER – OFFSET 300h ...................................132
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h .....................................132
RESERVED REGISTERS – OFFSET 308h TO 30Ch....................................................................133
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ......................................133
RESERVED REGISTERS – OFFSET 314h TO FFCh ...................................................................133
Page 11 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130