PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 93

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.26
PERICOM SEMICONDUCTOR - Confidential
SECONDARY COMMAND REGISTER – OFFSET 44h
Bit
31
Bit
0
1
2
3
4
5
6
7
8
9
Function
Primary
Configuration
Access Lockout
Function
I/O Space Enable
Memory Space
Enable
Bus Master Enable
Special Cycle
Enable
Memory Write and
Invalidate Enable
VGA Palette Snoop
Enable
Parity Error
Response Enable
Wait Cycle Control
Secondary SERR_L
Enable Bit
Fast Back-to-Back
Enable
Type
Type
RO / RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
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Description
0: PI7C9X130 configuration space can be accessed from both interfaces
1: PI7C9X130 configuration space can only be accessed from the secondary
interface. Primary bus accessed receives completion with CRS status for
forward bridge, or target retry for reverse bridge
Reset to 1 if TM0 is HIGH (the local host on secondary bus needs to program
this bit to 0 after the secondary configuration programming is completed in
non-transparent mode, otherwise there will be no configuration access from
primary interface)
Description
0: Ignore I/O transactions on the secondary interface
1: Enable response to memory transactions on the secondary interface
Reset to 0
0: Ignore memory read transactions on the secondary interface
1: Enable memory read transactions on the secondary interface
Reset to 0
0: Do not initiate memory or I/O transactions on the secondary interface and
disable response to memory and I/O transactions on the secondary interface
1: Enable the PI7C9X130 to operate as a master on the secondary interfaces
for memory and I/O transactions forwarded from the secondary interface. If
the secondary of the reverse bridge is PCI-X mode, the PI7C9X130 is allowed
to initiate a split completion transaction regardless of the status bit.
Reset to 0
0: Bridge does not respond as a target to Special Cycle transactions, so this
bit is defined as Read-Only and must return 0 when read
Reset to 0
0: PI7C9X130 does not originate a Memory Write and Invalidate transaction.
Implements this bit as Read-Only and returns 0 when read (unless forwarding a
transaction for another master). This bit will be ignored in PCI-X mode.
Reset to 0
0: Ignore VGA palette snoop access on the secondary
Reset to 0
0: May ignore any parity error that is detected and take its normal action
1: This bit if set, enables the setting of Master Data Parity Error bit in the
Status Register when poisoned TLP received or parity error is detected and
takes its normal action
Reset to 0
Wait cycle control not supported
Reset to 0
0: Disable
1: Enable PI7C9X130 in forward bridge mode to report non-fatal or fatal error
message to the Root Complex. Also, in reverse bridge mode to assert
SERR_L on the secondary interface
Reset to 0
Fast back-to-back enable not supported
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130