PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 97

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.30
7.5.31
PERICOM SEMICONDUCTOR - Confidential
ARBITER PRIORITY REGISTER – OFFSET 48h
SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch
Bit
22
23
24
25
26
27
28
29
30
31
Bit
1:0
2
3
4
5
Function
Arbiter Priority 0
Arbiter Priority 1
Arbiter Priority 2
Arbiter Priority 3
Arbiter Priority 4
Arbiter Priority 5
Arbiter Priority 6
Arbiter Priority 7
Arbiter Priority 8
Reserved
Function
Reserved
Cache Line Size
Cache Line Size
Cache Line Size
Cache Line Size
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
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Description
0: Low priority request to internal bridge
1: High priority request to internal bridge
Reset to 1
0: Low priority request to master 1
1: High priority request to master 1
Reset to 0
0: Low priority request to master 2
1: High priority request to master 2
Reset to 0
0: Low priority request to master 3
1: High priority request to master 3
Reset to 0
0: Low priority request to master 4
1: High priority request to master 4
Reset to 0
0: Low priority request to master 5
1: High priority request to master 5
Reset to 0
0: Low priority request to master 6
1: High priority request to master 6
Reset to 0
0: Low priority request to master 7
1: High priority request to master 7
Reset to 0
0: Low priority request to master 8
1: High priority request to master 8
Reset to 0
Reset to 0
Description
00: Cache line size of 1 DW and 2 DW are not supported
Reset to 00
1: Cache line size = 4 double words
Reset to 0
1: Cache line size = 8 double words
Reset to 0
1: Cache line size = 16 double words
Reset to 0
1: Cache line size = 32 double words
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130