PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 104

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.46
7.5.47
PERICOM SEMICONDUCTOR - Confidential
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET 74h
BRIDGE CONTROL AND STATUS REGISTER – OFFSET 78h
Bit
31:16
Bit
7:0
15:8
16
17
18
19
21:20
22
23
31:24
Bit
1:0
2
3
Function
EEPROM Data
Function
Capability ID for
Hot Swap
Next Capability
Pointer
Device Hiding Arm
ENUM_L signal
Mask
Pending Insertion or
Extraction
LED On Off
Programming
Interface
EXT for Extraction
INS for Insertion
Reserved
Function
Reserved
SERR_L Forward
Enable
Secondary Interface
Reset
Type
Type
Type
RW/RO
RWC
RWC
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
Page 104 of 165
Description
EEPROM data to be written into the EEPROM
Reset to 0000h
Description
Reset to 06h when Hot Sawp is enable (HS_EN=1) or 00h when Hot Swap is
disabled (HS_EN=0)
Reset to 00h to inidicate the end of the capability chain
Device Hiding Armed when this bit is set to 1
Reset to 0
ENUM_L signal is masked when this bit is set to 1
Reset to 0
When this bit is 1, INS is armed, or either INS or EXT has a value of logic 1
When this bit is 0, INS is not armed or both INS and EXT have a value of logic
0
Reset to 0h
When this bit is 1, LED is on
When this bit is 0, LED is off
Reset to 0
PI=01 supports PI=00 plus device hiding and pending insertion or extraction
bits
Reset to 01
EXT bit indicates ENUM_L status of extraction. When EXT is 1, ENUM_L
is asserted
Reset to 0
INS bit indicates ENUM_L status of insertion. When INS is 1, ENUM_L is
asserted
Reset to 1
Reset to 00h
Description
Reset to 00
0: Disable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
1: Enable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
Reset to 0 (FORWARD BRIDGE)
RO bit for REVERSE BRIDGE
0: Do not force the assertion of RESET_L on secondary PCI/PCI-X bus in
forward bridge mode, or do not generate a hot reset on the PCI Express link in
reverse bridge mode
1: Force the assertion of RESET_L on secondary PCI/PCI-X bus in forward
bridge mode, or generate a hot reset on the PCI Express link in reverse bridge
mode
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130