PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 8

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
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DEVICE CONTROL REGISTER – OFFSET B8h ...............................................................................65
DEVICE STATUS REGISTER – OFFSET B8h....................................................................................66
LINK CAPABILITY REGISTER – OFFSET BCh ................................................................................67
LINK CONTROL REGISTER – OFFSET C0h ....................................................................................67
LINK STATUS REGISTER – OFFSET C0h.........................................................................................68
SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................68
SLOT CONTROL REGISTER – OFFSET C8h ....................................................................................69
SLOT STATUS REGISTER – OFFSET C8h ........................................................................................69
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh ...................................................................69
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h....................................................................70
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h....................................................................70
HOT SWAP SWITCH DEBOUNCE COUNTER – OFFSET D4h .......................................................70
CAPABILITY ID REGISTER – OFFSET D8h .....................................................................................70
NEXT POINTER REGISTER – OFFSET D8h .....................................................................................71
VPD REGISTER – OFFSET D8h ........................................................................................................71
VPD DATA REGISTER – OFFSET DCh.............................................................................................71
EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h...........................71
EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h..................................71
RESERVED REGISTER - OFFSET E8h TO ECh................................................................................72
MESSAGE SIGNALED INTERRUPTS ID REGISTER – OFFSET F0h ..............................................72
NEXT CAPABILITIES POINTER REGISTER – OFFSET F0h ...........................................................72
MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................72
MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................72
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h ...............................................................73
MESSAGE DATA REGISTER – OFFSET FCh ...................................................................................73
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................74
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................74
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ...............................................................74
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ..................................................74
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................74
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch..........................................75
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h....................................................75
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h.......................................................76
ADVANCED ERROR CAPABILITIES & CONTROL REGISTER – OFFSET 118h........................76
HEADER LOG REGISTER 1 – OFFSET 11Ch...............................................................................76
HEADER LOG REGISTER 2 – OFFSET 120h................................................................................76
HEADER LOG REGISTER 3 – OFFSET 124h................................................................................77
HEADER LOG REGISTER 4 – OFFSET 128h................................................................................77
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch......................77
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h..........................78
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h...................78
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h ....................79
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h ..............................................79
RESERVED REGISTER – OFFSET 14Ch.......................................................................................79
VC CAPABILITY ID REGISTER – OFFSET 150h ..........................................................................79
VC CAPABILITY VERSION REGISTER – OFFSET 150h ..............................................................79
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ...........................................................80
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h .................................................................80
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h .................................................................80
PORT VC CONTROL REGISTER – OFFSET 15Ch .......................................................................80
PORT VC STATUS REGISTER – OFFSET 15Ch............................................................................80
VC0 RESOURCE CAPBILITY REGISTER – OFFSET 160h...........................................................81
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ............................................................81
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ................................................................81
Page 8 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130