PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 71

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.84 NEXT POINTER REGISTER – OFFSET D8h
7.4.85 VPD REGISTER – OFFSET D8h
7.4.86 VPD DATA REGISTER – OFFSET DCh
7.4.87 EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h
7.4.88 EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h
PERICOM SEMICONDUCTOR - Confidential
Bit
15:8
Bit
17:16
23:18
30:24
31
Bit
31:0
Bit
7:0
11:8
30:12
Bit
31:0
Function
Next Pointer
Function
Reserved
VPD Address for
Read/Write Cycle
Reserved
VPD Operation
Function
VPD Data
Function
Register Number
Extended Register
Number
Reserved
Function
Extended
Configuration
Access Data
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
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Description
Next pointer (F0h, points to MSI capabilities)
Reset to F0h
Description
Reset to 0
Reset to 0
Reset to 0
0: Generate a read cycle from the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘0’ until EEPROM cycle is finished,
after which the bit is then set to ‘1’. Data for reads is available at register ECh.
1: Generate a write cycle to the EEPROM at the VPD address specified in bits
[7:2] of offset D8h. This bit remains at ‘1’ until EEPROM cycle is finished,
after which it is then cleared to ‘0’.
Reset to 0
Description
VPD Data (EEPROM data [address + 0x40])
The least significant byte of this register corresponds to the byte of VPD at the
address specified by the VPD address register. The data read form or written to
this register uses the normal PCI byte transfer capabilities.
Reset to 0
Description
Reset to 00h
Reset to 0h
Reset to 0
Description
Access to this register will access the internal configuration registers indexed
by bit [11:0] at offset E0h
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130