PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 6

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
1
2
3
4
5
6
7
PERICOM SEMICONDUCTOR - Confidential
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.1
3.2
3.3
5.1
5.2
6.1
6.2
7.1
7.2
7.3
7.4
INTRODUCTION .............................................................................................................................................15
PIN DEFINITION .............................................................................................................................................17
MODE SELECTION AND PIN STRAPPING ...............................................................................................24
FORWARD AND REVERSE BRIDGING .....................................................................................................26
TRANSPARENT AND NON-TRANSPARENT BRIDGING .......................................................................27
PCI EXPRESS FUNCTIONAL OVERVIEW ................................................................................................29
CONFIGURATION REGISTERS...................................................................................................................31
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
PCI EXPRESS FEATURES ........................................................................................................................15
PCI/PCI-X FEATURES...............................................................................................................................16
GENERAL FEATURES..............................................................................................................................16
SIGNAL TYPES..........................................................................................................................................17
PCI EXPRESS SIGNALS............................................................................................................................17
PCI SIGNALS .............................................................................................................................................18
MODE SELECT AND STRAPPING SIGNALS.........................................................................................20
JTAG BOUNDARY SCAN SIGNALS .......................................................................................................20
MISCELLANEOUS SIGNALS ..................................................................................................................21
POWER AND GROUND PINS...................................................................................................................22
PIN ASSIGNMENT ....................................................................................................................................22
FUNCTIONAL MODE SELECTION.........................................................................................................24
PCI/PCI-X SELECTION .............................................................................................................................24
PIN STRAPPING ........................................................................................................................................25
TRANSPARENT MODE ............................................................................................................................27
NON-TRANSPARENT MODE ..................................................................................................................27
TLP STRUCTURE ......................................................................................................................................29
VIRTUAL ISOCHRONOUS OPERATION ...............................................................................................30
CONFIGURATION REGISTER MAP .......................................................................................................31
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP..................................................................36
CONTROL AND STATUS REGISTER MAP ............................................................................................37
PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE......................................39
VENDOR ID – OFFSET 00h ...............................................................................................................39
DEVICE ID – OFFSET 00h.................................................................................................................39
COMMAND REGISTER – OFFSET 04h.............................................................................................39
PRIMARY STATUS REGISTER – OFFSET 04h..................................................................................40
REVISION ID REGISTER – OFFSET 08h ..........................................................................................42
CLASS CODE REGISTER – OFFSET 08h..........................................................................................42
CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................42
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................42
HEADER TYPE REGISTER – OFFSET 0Ch ......................................................................................43
RESERVED REGISTERS – OFFSET 10h TO 17h ..............................................................................43
PRIMARY BUS NUMBER REGISTER – OFFSET 18h .......................................................................43
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................43
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................43
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h............................................................43
I/O BASE REGISTER – OFFSET 1Ch.................................................................................................43
I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................44
Page 6 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130