PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 111

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.63
7.5.64
7.5.65
PERICOM SEMICONDUCTOR - Confidential
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h
DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET 98h
DOWNSTREAM MEMORY 0 SETUP REGISTER – OFFSET 9Ch
Bit
14:13
15
Bit
21:16
22
23
31:24
Bit
11:0
31:12
Bit
0
2:1
3
11:4
30:12
31
Function
Data Scale
PME Status
Function
Reserved
B2/B3 Support
PCI Bus
Power/Clock Control
Data Register
Function
Reserved
Downstream
Memory 0
Translated Base
Function
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address
Register Size
Base Address
Register Enable
RO (WS)
RO (WS)
RO (WS)
RWCS
Type
Type
Type
Type
(WS)
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 111 of 165
Description
Data register is not implemented
Reset to 00
PME_L is supported
Reset to 0
Description
Reset to 000000
B2 / B3 not support for D3hot
Reset to 0
PCI Bus Power/Clock Disabled
Reset to 0
Data register is not implemented
Reset to 00h
Description
Reset to 000h
Define the translated base address for downstream memory transactions whose
initiator addresses fall into Downstream Memory 0 (above lower 4K boundary)
address range. The number of bits that are used for translated base is
determined by its setup register (offset 9Ch)
Reset to 00000h
Description
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00h
0: Set the corresponding bit in the Base Address Register to read only.
1: Set the corresponding bit in the Base Address Register to read/write in order
to control the size of the address range.
Reset to 7FFFFh
Always set to 1 when a bus master attempts to write a zero to this bit.
PI7C9X130 returns bit [31:12] as FFFFFh (for 4KB size).
Reset to 1
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130