PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 39

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4 PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE
7.4.1 VENDOR ID – OFFSET 00h
7.4.2 DEVICE ID – OFFSET 00h
7.4.3 COMMAND REGISTER – OFFSET 04h
PERICOM SEMICONDUCTOR - Confidential
MODE
The following section describes the configuration space when the device is in transparent mode. The
descriptions for different register type are listed as follow:
PCI Express /
PCI Memory
Offset
1FFh – 100h
FFFh – 200h
Register Type
RO
ROS
RW
RO(WS)
RWC
RWS
RWCS
Bit
15:0
Bit
31:16
Bit
0
1
2
Function
Vendor ID
Function
Device ID
Function
I/O Space Enable
Memory Space
Enable
Bus Master Enable
SM Bus
Offset
3FFh – 300h
11FFh – 400h
Type
Type
Type
RW
RW
RW
RO
RO
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Register
Name
Upstream
Memory 2
Lookup Table
Reserved
Descriptions
Read Only
Read Only and Sticky
Read/Write
Read Only at primary interface and Read/Write at secondary interface
Read/Write “1” to clear
Read/Write and Sticky
Read/Write “1” to clear and Sticky
Description
Identifies Pericom as the vendor of this device. Returns 12D8h when read.
Description
Identifies this device as the PI7C9X130. Returns E130 when read.
Description
0: Ignore I/O transactions on the primary interface
1: Enable response to memory transactions on the primary interface
Reset to 0
0: Ignore memory read transactions on the primary interface
1: Enable memory read transactions on the primary interface
Reset to 0
0: Do not initiate memory or I/O transactions on the primary interface and
disable response to memory and I/O transactions on the secondary interface
1: Enable the bridge to operate as a master on the primary interfaces for
memory and I/O transactions forwarded from the secondary interface. If the
primary of the reverse bridge is PCI-X mode, the bridge is allowed to initiate a
split completion transaction regardless of the status bit.
Reset to 0
Reset Value
0
0
PCI EXPRESS TO PCI-X BRIDGE
(I2C) Access
EEPROM
No
No
Mar 2010 - Rev 2.0
SM Bus
Access
Yes
Yes
PI7C9X130