PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 10

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
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BRIDGE CONTROL AND STATUS REGISTER – OFFSET 78h ......................................................104
GPIO DATA AND CONTROL REGISTER – OFFSET 78h...............................................................105
SECONDARY INTERRUPT LINE REGISTER – OFFSET 7Ch ........................................................105
SECONDARY INTERRUPT PIN REGISTER – OFFSET 7Ch ..........................................................106
SECONDARY MINIMUM GRANT REGISTER – OFFSET 7Ch .......................................................106
SECONDARY MAXIMUM LATENCY TIMER – OFFSET 7Ch ........................................................106
PCI-X CAPABILITY ID REGISTER – OFFSET 80h.........................................................................106
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h .............................................................106
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h...............................................................106
PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.......................................................................107
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h.....................................................109
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch..............................................109
POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................109
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h .............................................................109
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h ...............................................110
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h ...........................110
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h...................................111
DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET 98h.............................111
DOWNSTREAM MEMORY 0 SETUP REGISTER – OFFSET 9Ch ..................................................111
CAPABILITY ID REGISTER – OFFSET A0h....................................................................................112
NEXT POINTER REGISTER – OFFSET A0h ...................................................................................112
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................112
CHASSIS NUMBER REGISTER – OFFSET A0h ..............................................................................112
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h..............................112
DOWNSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET A8h................113
DOWNSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ACh .....................................114
CAPABILITY ID REGISTER – OFFSET B0h....................................................................................114
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h.............................................................114
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................114
DEVICE CAPABILITY REGISTER – OFFSET B4h..........................................................................115
DEVICE CONTROL REGISTER – OFFSET B8h .............................................................................116
DEVICE STATUS REGISTER – OFFSET B8h..................................................................................117
LINK CAPABILITY REGISTER – OFFSET BCh ..............................................................................117
LINK CONTROL REGISTER – OFFSET C0h ..................................................................................118
LINK STATUS REGISTER – OFFSET C0h.......................................................................................118
SLOT CAPABILITY REGISTER – OFFSET C4h ..............................................................................119
SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................119
SLOT STATUS REGISTER – OFFSET C8h ......................................................................................120
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh .................................................................120
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h..................................................................120
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h..................................................................121
CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................121
NEXT POINTER REGISTER – OFFSET D8h ...................................................................................121
VPD REGISTER – OFFSET D8h ......................................................................................................121
VPD DATA REGISTER – OFFSET DCh...........................................................................................121
UPSTREAM MEMORY 0 TRANSLATED BASE - OFFSET E0h.......................................................122
UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h .........................................................122
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h ......................122
UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh............................................122
MESSAGE SIGNALED INTERRUPTS ID REGISTER – OFFSET F0h ............................................123
NEXT CAPABILITY POINTER REGISTER – OFFSET F0h.............................................................123
MESSAGE CONTROL REGISTER – OFFSET F0h ..........................................................................123
MESSAGE ADDRESS REGISTER – OFFSET F4h ...........................................................................124
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h .........................................................124
Page 10 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130