PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 91

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.24
7.5.25
PERICOM SEMICONDUCTOR - Confidential
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h
CHIP CONTROL 0 REGISTER – OFFSET 40h
Bit
0
1
2
3
5:4
7:6
9:8
10
11
14:12
Bit
15
Function
Secondary Internal
Arbiter’s PARK
Function
Memory Read
Prefetching Dynamic
Control Disable
Completion Data
Prediction Control
Reserved
Reserved
Reserved
PCI Read Prefetch
Mode
PCI Special Delayed
Read Mode Enable
Reserved
Maximum Memory
Read Byte Count
Function
Flow Control Update
Control
Type
Type
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Page 91 of 165
Description
0: Park to the last master
1: Park to PI7C9X130 secondary port
Reset to 0
0: Enable memory read prefetching dynamic control for PCI to PCIe read
1: Disable memory read prefetching dynamic control for PCI to PCIe read
Reset to 0
0: Enable completion data prediction for PCI to PCIe read.
1: Disable completion data prediction
Reset to 0
Reset to 0
Reset to 11
Reset to 11
00: One cache line prefetch if memory read address is in prefetchable range at
PCI interface
01: Reserved
10: Full prefetch if memory read address is in prefetchable range at PCI
interface
11: Disconnect on the first DWORD
Reset to 00
0: Retry any master at PCI bus that repeats its transaction with command
code changes.
1: Allows any master at PCI bus to change memory command code (MR,
MRL, MRM) after it has received a retry. The PI7C9X130 will complete the
memory read transaction and return data back to the master if the address and
byte enables are the same.
Reset to 0
Reset to 0
Maximum byte count is used by the PI7C9X130 when generating memory read
requests on the PCIe link in response to a memory read initiated on the PCI bus
and bit [9:8], bit [7:6], and bit [5:4] are set to “full prefetch”.
000: 512 bytes
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
101: 2048 bytes
110: 4096 bytes
111: 512 bytes
Reset to 000
Description
0: Flow control is updated for every two credits available
1: Flow control is updated for every on credit available
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130