PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 84

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.3
PERICOM SEMICONDUCTOR - Confidential
PRIMARY STATUS REGISTER – OFFSET 04h
Bit
5
6
7
8
9
10
15:11
Bit
18:16
19
20
21
22
23
Function
VGA Palette Snoop
Enable
Parity Error
Response Enable
Wait Cycle Control
Primary SERR_L
Enable Bit
Fast Back-to-Back
Enable
Primary Interrupt
Disable
Reserved
Function
Reserved
Primary Interrupt
Status
Capability List
Capable
66MHz Capable
Reserved
Fast Back-to-Back
Capable
Type
Type
RO / RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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Description
0: Ignore VGA palette snoop access on the primary
Reset to 0
0: May ignore any parity error that is detected and take its normal action
1: This bit if set, enables the setting of Master Data Parity Error bit in the
Status Register when poisoned TLP received or parity error is detected and
takes its normal action
Reset to 0
Wait cycle control not supported
Reset to 0
0: Disable
1: Enable PI7C9X130 in forward bridge mode to report non-fatal or fatal error
message to the Root Complex. Also, in reverse bridge mode to assert
SERR_L on the primary interface
Reset to 0
Fast back-to-back enable not supported
Reset to 0
0: INTx interrupt messages can be generated
1: Prevent INTx messages to be generated and any asserted INTx interrupts
will be released.
Reset to 0
Reset to 00000
Description
Reset to 000
0: No INTx interrupt message request pending in PI7C9X130 primary
1: INTx interrupt message request pending in PI7C9X130 primary
Reset to 0
1: PI7C9X130 supports the capability list (offset 34h in the pointer to the data
structure)
Reset to 1
This bit applies to reverse bridge only.
1: 66MHz capable
Reset to 0 when forward bridge or 1 when reverse bridge.
Reset to 0
This bit applies to reverse bridge only.
1: Enable fast back-to-back transactions
Reset to 0 when forward bridge or 1 when reverse bridge with primary bus in
PCI mode
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130