PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 7

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
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SECONDARY STATUS REGISTER – OFFSET 1Ch ...........................................................................44
MEMORY BASE REGISTER – OFFSET 20h ......................................................................................45
MEMORY LIMIT REGISTER – OFFSET 20h .....................................................................................45
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h........................................................45
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h.......................................................46
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h ...............................................46
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch..............................................46
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h........................................................................46
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h........................................................................46
CAPABILITY POINTER – OFFSET 34h .............................................................................................46
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h......................................................47
INTERRUPT LINE REGISTER – OFFSET 3Ch..................................................................................47
INTERRUPT PIN REGISTER – OFFSET 3Ch....................................................................................47
BRIDGE CONTROL REGISTER – OFFSET 3Ch ...............................................................................47
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h......................................................48
CHIP CONTROL 0 REGISTER – OFFSET 40h..................................................................................50
RESERVED REGISTER – OFFSET 44h .............................................................................................51
ARBITER ENABLE REGISTER – OFFSET 48h..................................................................................51
ARBITER MODE REGISTER – OFFSET 48h.....................................................................................52
ARBITER PRIORITY REGISTER – OFFSET 48h ...............................................................................52
RESERVED REGISTERS – OFFSET 4Ch TO 64h..............................................................................53
EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER – OFFSET 68h................................53
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ......................54
RESERVED REGISTER – OFFSET 6Ch.............................................................................................54
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h..........................................54
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET 74h ...................................................55
GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................56
RESERVED REGISTER – OFFSET 7Ch.............................................................................................56
PCI-X CAPABILITY ID REGISTER – OFFSET 80h...........................................................................56
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ...............................................................56
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h.................................................................56
PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.........................................................................57
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h.......................................................58
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch................................................59
POWER MANAGEMENT ID REGISTER – OFFSET 90h...................................................................59
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ...............................................................59
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................59
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................60
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h.....................................60
RESERVED REGISTERS – OFFSET 98h TO 9Ch..............................................................................61
CAPABILITY ID REGISTER – OFFSET A0h......................................................................................61
NEXT POINTER REGISTER – OFFSET A0h .....................................................................................61
SLOT NUMBER REGISTER – OFFSET A0h ......................................................................................61
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................61
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................62
CAPABILITY ID REGISTER – OFFSET A8h......................................................................................63
NEXT POINTER REGISTER – OFFSET A8h .....................................................................................63
RESERVED REGISTER – OFFSET A8h .............................................................................................63
SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh.....................................................................63
SUBSYSTEM ID REGISTER – OFFSET ACh .....................................................................................63
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................63
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h...............................................................64
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ..................................................................64
DEVICE CAPABILITY REGISTER – OFFSET B4h............................................................................64
Page 7 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130