PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 9

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
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PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE............................83
VENDOR ID – OFFSET 00h ...............................................................................................................83
DEVICE ID – OFFSET 00h.................................................................................................................83
PRIMARY COMMAND REGISTER – OFFSET 04h ...........................................................................83
PRIMARY STATUS REGISTER – OFFSET 04h..................................................................................84
REVISION ID REGISTER – OFFSET 08h ..........................................................................................85
CLASS CODE REGISTER – OFFSET 08h..........................................................................................86
PRIMARY CACHE LINE SIZE REGISTER – OFFSET 0Ch ...............................................................86
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................86
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch .....................................................................86
PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 10h...............................87
PRIMARY CSR IO BASE ADDRESS REGISTER – OFFSET 14h.......................................................87
DOWNSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 18h ..........................87
DOWNSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 1Ch .....................................88
DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h......................................88
DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 24h ........................89
RESERVED REGISTER – OFFSET 28h .............................................................................................89
SUBSYSTEM ID AND SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch ................................89
RESERVED REGISTER – OFFSET 30h .............................................................................................89
CAPABILITY POINTER – OFFSET 34h .............................................................................................89
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h......................................................90
PRIMARY INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................90
PRIMARY INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................90
PRIMARY MINIMUM GRANT REGISTER – OFFSET 3Ch ...............................................................90
PRIMARY MAXIMUM LATNECY TIMER – OFFSET 3Ch ................................................................90
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h......................................................91
CHIP CONTROL 0 REGISTER – OFFSET 40h..................................................................................91
SECONDARY COMMAND REGISTER – OFFSET 44h .....................................................................93
SECONDARY STATUS REGISTER – OFFSET 44h............................................................................94
ARBITER ENABLE REGISTER – OFFSET 48h..................................................................................95
ARBITER MODE REGISTER – OFFSET 48h.....................................................................................96
ARBITER PRIORITY REGISTER – OFFSET 48h ...............................................................................97
SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch .........................................................97
SECONDARY LATENCY TIMER REGISTER – OFFSET 4Ch ...........................................................98
SECONDARY HEADER TYPE REGISTER – OFFSET 4C .................................................................98
SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 50h.........................98
SECONDARY CSR IO BASE ADDRESS REGISTER – OFFSET 54h.................................................99
UPSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 58h.................................99
UPSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 5Ch ...........................................99
UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h ..........................................100
UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 64h.............................100
EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER – OFFSET 68h..............................101
MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h ...............................102
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................102
SUBSYSTEM VENDOR ID REGISTER – OFFSET 6Ch ...................................................................103
SUBSYSTEM ID REGISTER – OFFSET 6Ch....................................................................................103
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................103
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET 74h .................................................104
RESERVED REGISTERS – OFFSET 16Ch TO 2FCh.....................................................................81
EXTENDED GPIO DATA AND CONTROL REGISTER – OFFSET 300h .....................................81
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h .......................................82
RESERVED REGISTERS – OFFSET 308h TO 30Ch......................................................................82
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ........................................82
RESERVED REGISTERS – OFFSET 314h TO FFCh .....................................................................82
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PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130