PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 50

IC PCIE-PCIX BRIDGE 1PORT 256BGA

PI7C9X130DNDE

Manufacturer Part Number
PI7C9X130DNDE
Description
IC PCIE-PCIX BRIDGE 1PORT 256BGA
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X130DNDE

Applications
PCI-to-PCI Bridge
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
1.8V, 3.3V
Package / Case
256-PBGA
Mounting Type
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X130DNDE
Manufacturer:
Pericom
Quantity:
135
Part Number:
PI7C9X130DNDE
Manufacturer:
NSC
Quantity:
70
Part Number:
PI7C9X130DNDE
Manufacturer:
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Quantity:
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7.4.32 CHIP CONTROL 0 REGISTER – OFFSET 40h
PERICOM SEMICONDUCTOR - Confidential
Bit
15
16
18:17
19
20
22:21
23
25:24
26
29:27
30
Function
Flow Control Update
Control
PCI Retry Counter
Status
PCI Retry Counter
Control
PCI Discard Timer
Disable
PCI Discard Timer
Short Duration
Configuration
Request Retry Timer
Counter Value
Control
Delayed Transaction
Order Control
Completion Timer
Counter Value
Control
Isochronous Traffic
Support Enable
Traffic Class Used
For Isochronous
Traffic
Serial Link Interface
Loopback Enable
Type
RW / RO
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 50 of 165
Description
0: Flow control is updated for every two credits available
1: Flow control is updated for every on credit available
Reset to 0
0: The PCI retry counter has not expired since the last reset
1: The PCI retry counter has expired since the last reset
Reset to 0
00: No expiration limit
01: Allow 256 retries before expiration
10: Allow 64K retries before expiration
11: Allow 2G retries before expiration
Reset to 00
0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge
control register)
1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge
control register)
Reset to 0
0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse
bridge to indicate how many PCI clocks should be allowed before the PCI
discard timer expires
1: 64 PCI clocks allowed before the PCI discard timer expires
Reset to 0
00: Timer expires at 25us
01: Timer expires at 0.5ms
10: Timer expires at 5ms
11: Timer expires at 25ms
Reset to 01
0: Enable out-of-order capability between delayed transactions
1: Disable out-of-order capability between delayed transactions
Reset to 0
00: Timer expires at 50us
01: Timer expires at 10ms
10: Timer expires at 50ms
11: Timer disabled
Reset to 01
0: All memory transactions from PCI-X to PCIe will be mapped to TC0
1: All memory transactions from PCI-X to PCIe will be mapped to Traffic
Class defined in bit [29:27] of offset 40h.
Reset to 0
Reset to 001
0: Normal mode
1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW,
TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI
transaction from PCI bus will loop back to PCI bus
RO for forward bridge
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130

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