PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 79

IC PCIE-PCIX BRIDGE 1PORT 256BGA

PI7C9X130DNDE

Manufacturer Part Number
PI7C9X130DNDE
Description
IC PCIE-PCIX BRIDGE 1PORT 256BGA
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X130DNDE

Applications
PCI-to-PCI Bridge
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
1.8V, 3.3V
Package / Case
256-PBGA
Mounting Type
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X130DNDE
Manufacturer:
Pericom
Quantity:
135
Part Number:
PI7C9X130DNDE
Manufacturer:
NSC
Quantity:
70
Part Number:
PI7C9X130DNDE
Manufacturer:
Pericom
Quantity:
10 000
7.4.112SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h
7.4.113SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h
7.4.114RESERVED REGISTER – OFFSET 14Ch
7.4.115VC CAPABILITY ID REGISTER – OFFSET 150h
7.4.116VC CAPABILITY VERSION REGISTER – OFFSET 150h
PERICOM SEMICONDUCTOR - Confidential
Bit
9
10
11
12
13
31:14
Bit
4:0
31:5
Bit
35:0
39:36
43:40
63:44
95:64
127:96
Bit
15:0
Function
Uncorrectable
Address Error
Severity
Delayed Transaction
Discard Timer
Expired Severity
PERR_L Assertion
Detected Severity
SERR_L Assertion
Detected Severity
Internal Bridge Error
Severity
Reserved
Function
Secondary First
Error Pointer
Reserved
Function
Transaction
Attribute
Transaction
Command Lower
Transaction
Command Upper
Reserved
Transaction Address
Transaction Address
Function
VC Capability ID
Type
Type
Type
Type
ROW
RWS
RWS
RWS
RWS
RWS
ROS
ROS
ROS
ROS
ROS
ROS
RO
RO
RO
Page 79 of 165
Description
Reset to 1
Reset to 0
Reset to 0
Reset to 1
Reset to 0
Reset to 0
Description
Reset to 0
Reset to 0
Description
Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase
Reset to 0
Transaction command lower, CBE [3:0] during first address phase
Reset to 0
Transaction command upper, CBE [3:0] during second address phase of DAC
transaction
Reset to 0
Reset to 0
Transaction address, AD [31:0] during first address phase
Reset to 0
Transaction address, AD [31:0] during second address phase of DAC
transaction
Reset to 0
Description
Reset to 0002h
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130

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