TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 97

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

31-15
14-12
11-0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
7.6.2.5
Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources".
SETENA
-
SETENA
Bit Symbol
(Interrupt 31)
(Interrupt 15)
(Interrupt 23
(Interrupt 7)
SETENA
SETENA
SETENA
SETENA
Interrupt Set-Enable Register 1
31
23
15
0
0
0
7
0
R/W
R/W
R/W
Type
(Interrupt 30)
(Interrupt 22)
(Interrupt 6)
SETENA
SETENA
SETENA
30
22
14
0
0
0
6
0
Interrupt number [31:15]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write "0".
Interrupt number [11:0]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
-
(Interrupt 29)
(Interrupt 21)
(Interrupt 5)
SETENA
SETENA
SETENA
29
21
13
0
0
0
5
0
-
(Interrupt 28)
(Interrupt 20)
(Interrupt 4)
SETENA
SETENA
SETENA
Page 77
28
20
12
0
0
0
4
0
-
(Interrupt 27)
(Interrupt 19)
(Interrupt 11)
(Interrupt 3)
SETENA
SETENA
SETENA
SETENA
27
19
11
Function
0
0
0
3
0
(Interrupt 26)
(Interrupt 18)
(Interrupt 10)
(Interrupt 2)
SETENA
SETENA
SETENA
SETENA
26
18
10
0
0
0
2
0
TMPM333FDFG/FYFG/FWFG
(Interrupt 25)
(Interrupt 17)
(Interrupt 9)
(Interrupt 1)
SETENA
SETENA
SETENA
SETENA
25
17
0
0
9
0
1
0
(Interrupt 24)
(Interrupt 16)
(Interrupt 8)
(Interrupt 0)
SETENA
SETENA
SETENA
SETENA
24
16
0
0
8
0
0
0