TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 278

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.16
Operation in Each Mode
10.16.1.2
(1)
Receive
The SCLK output can be started by setting the receive enable bit SCxMOD0<RXE> to "1".
SCLK Output Mode
・ If double buffer is disabled (SCxMOD2<WBUF> = "0")
・ If double buffer is enabled (SCxMOD2<WBUF> = "1")
each time the CPU reads received data. When all the 8 bits are received, the INTRXx interrupt
is generated.
receive the next frame. A data is moved from the shift register to the receive buffer, the receive
buffer full flag SCxMOD2<RBFLL> is set to "1" and the INTRXx is generated.
completing reception of the next 8 bits, the INTRXx interrupt is not generated and the SCLK
output stops. In this state, reading data from the receive buffer allows data in the shift register
to move to the receive buffer and thus the INTRXx interrupt is generated and data reception
resumes.
A clock pulse is outputted from the SCLK pin and the next data is stored into the shift register
Data stored in the shift register is moved to the receive buffer and the receive buffer can
While data is in the receive buffer, if the data cannot be read from the receive buffer before
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TMPM333FDFG/FYFG/FWFG