TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 204

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TMPM333FDFG

Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM333FDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM333FDFG
Manufacturer:
Toshiba
Quantity:
10 000
9.2
Differences in the Specifications
9.2
Table 9-1 Differences in the Specifications of TMRB Modules
Specification
Channel
TMRB0
TMRB1
TMRB2
TMRB3
TMRB4
TMRB5
TMRB6
TMRB7
TMRB8
TMRB9
specification as shown in Table 9-1.
Differences in the Specifications
TMPM333FDFG/FYFG/FWFG contains 10-channel of TMRB.
Each channel functions independently and the channels operate in the same way except for the differences in their
Some of the channels can put the capture trigger and the synchronous start trigger on other channels.
1. The flip-flop output of TMRB 7 through TMRB 9 can be used as the capture trigger of other channels.
2. The start trigger of the timer synchronous mode (with TBxRUN)
・ TB7OUT → available for TMRB0 through TMRB1
・ TB8OUT → available for TMRB2 through TMRB4
・ TB9OUT → available for TMRB5 through TMRB6
・ TMRB0 → can start TMRB0 through TMRB3 synchronously
・ TMRB4 → can start TMRB4 through TMRB7 synchronously
TB0IN0
TB0IN1
TB1IN0
TB1IN1
TB2IN0
TB2IN1
TB3IN0
TB3IN1
TB4IN0
TB4IN1
TB5IN0
TB5IN1
TB6IN0
TB6IN1
capture trigger input pins
Signal
External clock/
(Pin number)
PH0 (30)
PH1 (31)
PH2 (32)
PH3 (36)
PH5 (10)
PH6 (84)
PH7 (85)
PD0 (95)
PD1 (96)
PD2 (97)
PD3 (98)
PH4 (9)
PI6 (79)
PI7 (83)
Port
External pins
TB0OUT
TB1OUT
TB2OUT
TB3OUT
TB4OUT
TB5OUT
TB6OUT
TB7OUT
TB8OUT
TB9OUT
Timer flip-flop output pin
Signal
(Pin number)
Page 184
PG7 (11)
PJ4 (88)
PI0 (38)
PI1 (40)
PI2 (42)
PI3 (48)
PI4 (52)
PI5 (53)
PK2 (7)
PJ5 (8)
Port
Trigger function between timers
TB7OUT
TB7OUT
TB8OUT
TB8OUT
TB8OUT
TB9OUT
TB9OUT
Capture
trigger
Synchronous
start trigger
channel
TMRB0
TMRB0
TMRB0
TMRB4
TMRB4
TMRB4
TMPM333FDFG/FYFG/FWFG
INTCAP00
INTCAP01
INTCAP10
INTCAP11
INTCAP20
INTCAP21
INTCAP30
INTCAP31
INTCAP40
INTCAP41
INTCAP50
INTCAP51
INTCAP60
INTCAP61
interrupt
Capture
Interrupt
interrupt
INTTB0
INTTB1
INTTB2
INTTB3
INTTB4
INTTB5
INTTB6
INTTB7
INTTB8
INTTB9
TMRB

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