TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 38

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

2.3
Exceptions/ Interruptions
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers.
clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product,
when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this
value is read as "0" both of <NOREF> bit and <SKEW> bit, it indicates that external reference clock are available
and the calibration value is accurate as 10ms.
and Reset Control Register are set.
included in software.
use non-maskable interruput (NMI) or reset.
software.
always "0x0000_0000" is read out.
Number of Priority Level Interrupt Bits
SysTick
SYSRESETREQ
LOCKUP
Auxiliary Fault Status register
The Cortex-M3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits.
TMPM333FDFG/FYFG/FWFG has three priority level interrupt bits. The number of priority level interrupt
The Cortex-M3 core has a SysTick timer which can generate SysTick exception.
In the TMPM333FDFG/FYFG/FWFG, the clock that is input from X1 pin dividing by 32 is used as a count
The Cortex-M3 core outputs SYSRESETREQ signal when <SYSRESETREQ> bit of Application Interrupt
TMPM333FDFG/FYFG/FWFG provides the same operation when SYSRESETREQ signal are output.
When irreparable exception generates, the Cortex-M3 core outputs LOCKUP signal to show a serious error
TMPM333FDFG/FYFG/FWFG does not use this signal. To return from LOCKUP status, it is necessary to
The Cortex-M3 core provides auxiliary fault status registers to supply additional system fault information to
However, TMPM333FDFG/FYFG/FWFG is not defined this function. If auxiliary fault status register is read,
Note:Do not reset with <SYSRESETREQ> in SLOW mode.
Page 18
TMPM333FDFG/FYFG/FWFG