TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 76

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.1
Overview
7.1.2
7.1.2.1
Return from exception
Handling by CPU
Execution of ISR
Branch to ISR
Detection by
Processing
CG/CPU
Handling Flowchart
Each step is described later in this chapter.
(1)
Exception Request and Detection
The following shows how an exception/interrupt is handled. In the following descriptions,
from external interrupt pins or peripheral functions.
condition occurs during instruction execution.
violation to the Fault region.
that are used for releasing a standby mode, relevant settings must be made in the clock generator.For
details, refer to "7.5 Interrupts".
Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests
An exception occurs when the CPU executes an instruction that causes an exception or when an error
An exception also occurs by an instruction fetch from the Execute Never (XN) region or an access
An interrupt request is generated from an external interrupt pin or peripheral function.For interrupts
Exception occurrence
The CG/CPU detects the exception request.
The CPU handles the exception request.
The CPU branches to the corresponding interrupt service routine (ISR).
Necessary processing is executed.
The CPU branches to another ISR or returns to the previous program.
indicates hardware handling.
Page 56
Description
Indicates software handling.
TMPM333FDFG/FYFG/FWFG
Section 7.1.2.1
Section 7.1.2.2
Section 7.1.2.3
Section 7.1.2.4
See