TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 267
TMPM333FDFG
Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Specifications of TMPM333FDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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Price
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10.12.3.2
Transmit shift register(INTTXx)
Figure 10-7 Operation of Transmission Buffer (Double-buffer is enabled)
transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and start
transmission. If data exists in the FIFO, the data is moved to the transmit buffer immediately, and the
<TBEMP> flag is cleared to "0".
as below.
transmit buffer or FIFO, and setting the SCxMOD1<TXE> bit to "1". When the last transmit data is moved
to the transmit buffer, the transmit FIFO interrupt is generated. When transmission of the last data is completed,
the clock is stopped and the transmission sequence is terminated.
lasts by writing transmit data.
SCxMOD1[6:5] =10
SCxFCNF[4:0] = 11011
SCxTFC[1:0] = 00
SCxTFC[7:6] = 11
When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and FIFO. Once
Settings and operations to transmit 4-byte data stream by setting the transfer mode to half duplex are shown
After above settings are configured, data transmission can be initiated by writing 5 bytes of data to the
Once above settings are configured, if the transmission is not set as auto disabled, the transmission should
Note:To use TX FIFO buffer, TX FIFO must be cleared after setting the SIO transfer mode (half duplex/
Transmit shift register
SCxMOD2<TBEMP>
Transmit FIFO Operation
full duplex) and enabling FIFO (SCxFCNF<CNFG> = "1").
Transmit buffer
Write data
: Transfer mode is set to half duplex.
: Transmission is automatically disabled if FIFO becomes empty.
: Sets the interrupt generation fill level to "0".
: Clears receive FIFO and sets the condition of interrupt generation.
The number of bytes to be used in the receive FIFO is the same as the interrupt
generation fill level.
Page 247
DATA 1
DATA 1
DATA 2
TMPM333FDFG/FYFG/FWFG
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