TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 216

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

9.5
Description of Operations for Each Circuit
9.5
9.5.1
Table 9-2 Prescaler Output Clock Resolutions(fc = 40MHz)
Description of Operations for Each Circuit
The channels operate in the same way, except for the differences in their specifications as shown in Table 9-1 .
peripheral clock
by CGSYSCR<PRCK[2:0]> in the CG.The peripheral clock, fperiph, is either fgear, a clock selected by
CGSYSCR<FPSEL> in the CG, or fc, which is a clock before it is divided by the clock gear.
and writing "0" clears and stops counting. Table 9-2 and Table 9-3 show prescaler output clock resolutions.
CGSYSCR
<FPSEL>
Prescaler
0 (fgear)
There is a 4-bit prescaler to generate the source clock for up-counter UC.
The prescaler input clock φT0 is fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected
The operation or the stoppage of a prescaler is set with TBxRUN<TBPRUN> where writing "1" starts counting
Select
Clock gear value
<GEAR[2:0]>
CGSYSCR
100 (fc/2)
101 (fc/4)
110 (fc/8)
000 (fc)
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
prescaler clock
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
<PRCK[2:0]>
CGSYSCR
Select
Page 196
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
1
9
2
3
4
5
6
2
3
4
5
6
7
3
4
5
6
7
8
4
5
6
7
8
φT1
(0.05 μs)
(12.8 μs)
(0.1 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(0.1 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
Prescaler output clock function
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
10
10
11
9
9
9
3
4
5
6
7
8
4
5
6
7
8
5
6
7
8
6
7
8
φT4
(12.8 μs)
(12.8 μs)
(12.8 μs)
(25.6 μs)
(25.6 μs)
(51.2 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
TMPM333FDFG/FYFG/FWFG
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
12
12
13
10
10
11
10
11
10
11
9
9
9
9
5
6
7
8
6
7
8
7
8
8
φT16
(102.4 μs)
(102.4 μs)
(204.8 μs)
(12.8 μs)
(12.8 μs)
(12.8 μs)
(12.8 μs)
(25.6 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(3.2 μs)
(6.4 μs)
(6.4 μs)