TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 310

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TMPM333FDFG

Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM333FDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM333FDFG
Manufacturer:
Toshiba
Quantity:
10 000
11.6
Data Transfer Procedure in the I2C Bus ModeI2C
INTSBIx
interrupt request
SCLx pin
SDAx pin
<PIN>
INTSBIx interrupt (after data transmission)
INTSBIx interrupt (first to (N-2)th data reception)
INTSBIx interrupt ((N-1)th data reception)
INTSBIx interrupt (Nth data reception)
INTSBIx interrupt (after completing data reception)
Figure 11-12 Terminating Data Transmission in the Master Receiver Mode
SBIxCR1
Reg.
End of interrupt
Reg.
End of interrupt
SBIxCR1
Reg.
End of interrupt
SBIxCR1
Reg.
End of interrupt
Processing to generate the stop condition.
End of interrupt
to terminate the data transfer.
In the interrupt processing for terminating the reception of 1-bit data, the stop condition is generated
9
Example: When receiving N data word
Note:X; Don’t care
D7
7
X
SBIxDBR
7
SBIxDBR
7
X
SBIxDBR
7
0
SBIxDBR
1
Read receive data aftwer clear <ACK> to “0”
6
X
6
6
X
6
0
D6
5
X
5
5
X
5
1
2
4
X
4
4
0
4
0
D5
3
3
0
3
3
0
3
0
2
X
2
2
X
2
X
D4
4
1
X
1
1
X
1
X
Page 290
0
X
0
0
X
0
X
D3
5
Sets the number of bits of data to be received and
specify whether ACK is required.
Reads dummy data.
Reads the first to (N-2)th data words.
Disables generation of acknowledgement clock.
Reads the (N-1)th data word.
Disables generation of acknowledgement clock.
Reads the Nth data word.
Terminates the data transmission.
D2
6
D1
7
D0
8
Read receive data after
set <BC[2:0]> to “001”.
TMPM333FDFG/FYFG/FWFG
1
Master output
Slave output
Acknowlegment signal to
transmitter “High”

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