TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 307
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TMPM333FDFG
Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Specifications of TMPM333FDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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SCLx pin
SDAx pin
<PIN>
INTSBIx
Interrupt request
11.6.2.2
Settings in main routine
Reg.
Reg.
if Reg.
Then
SBIxCR1
SBIxDR1
SBIxCR2
bit from the master device during the first eight clocks on the SCL line.
address, the SBI pulls the SDA line to the "Low" level during the ninth clock and outputs an acknowledgment
signal.
In the slave mode, the SBI holds the SCL line at the "Low" level while <PIN> is "0".
Figure 11-9 Generation of the Start Condition and a Slave Address
In the slave mode, the SBI receives the start condition and a slave address.
After receiving the start condition from the master device, the SBI receives a slave address and a direction
If the received address matches its slave address specified at SBIxI2CAR or is equal to the general-call
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to "0".
Slave mode
←
←
←
Example of INTSBI0 interrupt routine
←
←
≠
Start condition
7
SBIxSR
Reg. e 0x20
0x00
X
X
1
Clears the interrupt request.
Processing
End of interrupt
A6
6
X
X
1
1
5
X
X
1
A5
2
4
1
X
1
3
0
X
1
A4
3
2
X
X
0
Slave address + Direction bit
1
X
X
0
Page 287
A3
4
0
X
X
0
A2
5
Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
A1
6
A0
7
R/W
TMPM333FDFG/FYFG/FWFG
8
ACK
9
Master output
Slave output
Acknowledgement from
slave device
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