TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 358

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Description of Operations
Table 12-1 Relations in conversion modes, interrupt generation timings and flag operations
Table 12-2 Relation between analog channels input and AD conversion result registers
conversion
12.4.5.7
Analog input
Normal
channels
AIN10
AIN11
Top-priority conversion
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
Conversion mode
and flag operations. Table 12-2 shows a relation between analog channel inputs and AD conversion result
registers.
Fixed-channel
single conversion
Fixed-channel
repeat conversion
Channel scan
single conversion
Channel scan
repeat conversion
Table 12-1 shows a relation in the following three items: AD conversion modes, interrupt generation timings
Note:ADMOD0<EOCFN> and ADMOD2<EOCFHP> are cleared upon read.
Note:To access the conversion result register, use a half-word or a word access.
Other conversion mode
shown on the right side
Interrupt generation timings and AD conversion result storage register
ADREG2A
ADREG3B
ADREG4C
ADREG5D
ADREG6E
ADREG7F
ADREG2A
ADREG3B
than those
ADREG08
ADREG19
ADREG08
ADREG19
<REPEAT>
0
1
0
1
−
Scan/repeat mode setting
(every one conversion)
Fixed channel repeat
conversion mode
ADREG08 fixed
(ADMOD0)
<SCAIN>
0
0
1
1
−
Normal AD conversion
<ITM[1:0]>
Page 338
00
01
10
−
−
−
−
Fixed channel repeat
(every four conver-
ADREG3B
ADREG08
conversion mode
generation timing
After completion
After generation
Each time eight
After scan con-
↓
↓
sions)
Each time one
Each time four
After one scan
is completed.
conversion is
conversion is
conversion is
is completed.
conversion is
is completed.
completed.
completed.
completed.
completed.
Interrupt
version
Fixed channel repeat
After one scan con-
After conversion is
After eight conver-
After scan conver-
(every eight conver-
sion is completed.
sion is completed.
version is comple-
sions are comple-
sions are comple-
After one conver-
After four conver-
Conversion com-
ADREG7F
ADREG08
conversion mode
<EOCFHP>
<EOCFN>/
completed.
(See note)
set timing
pletion
↓
↓
↓
sions)
ted.
ted.
ted.
TMPM333FDFG/FYFG/FWFG
generated)
interrupt is
<ADBFN>
ADMOD0
(After the
Top-priority AD conver-
0
1
1
1
0
1
−
ADREGSP
sion
<ADBFHP>
ADMOD2
−
−
−
−
−
−
0