TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 362

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.2
Register
13.2
13.2.1
31-8
7
6-4
3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
The followings are the watchdog timer control registers and addresses.
Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI).
Register
Watchdog Timer Mode Register
Watchdog Timer Control Register
−
WDTE
WDTP[2:0]
−
I2WDT
RESCR
−
Bit Symbol
WDMOD(Watchdog Timer Mode Register)
WDTE
31
23
15
0
0
0
7
1
-
-
-
R
R/W
R/W
R
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
-
-
-
Read as 0.
Enable/Disable control
0:Disable
1:Enable
Selects WDT detection time(Refer toTable 13-1)
000: 2
001: 2
010: 2
011: 2
Read as 0.
Operation when IDLE mode
0: Stop
1:In operation
Operation after detecting malfunction
0: INTWDT interrupt request generates. (Note)
1: Reset
Write 0.
15
17
19
21
/fsys
/fsys
/fsys
/fsys
Register name
WDTP
29
21
13
0
0
0
5
0
-
-
-
Page 342
28
20
12
0
0
0
4
0
-
-
-
100: 2
101: 2
110:Setting prohibited.
111:Setting prohibited.
23
25
/fsys
/fsys
WDMOD
WDCR
27
19
11
Function
0
0
0
3
0
-
-
-
-
I2WDT
26
18
10
0
0
0
2
0
-
-
-
Base Address = 0x4004_0000
TMPM333FDFG/FYFG/FWFG
Address(Base+)
0x0000
0x0004
RESCR
25
17
0
0
9
0
1
1
-
-
-
24
16
0
0
8
0
0
0
-
-
-
-