TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 431

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(3)
(4)
(5)
completed.
BSY> . While no automatic verify operation is performed internally to the device, be sure to read the
data to confirm that data has been correctly erased. Any new command sequence is not accepted while
it is in an automatic block erase operation. If it is desired to stop operation, use the hardware reset
function. In this case, it is necessary to perform the automatic block erase operation again because the
data erasing operation has not been normally terminated.
flash memory is locked in the mode and will not return to the read mode. In this case, execute hardware
reset to reset the device.
15-18 for table of protection bit addresses. This device assigns 1 bit to 1 block as a protection bit. The
applicable protection bit is specified by PBA in the seventh bus write cycle. By automatically program-
ming the protection bits, write and/or erase functions can be inhibited (for protection) individually for
each block. The protection status of each block can be checked by FCFLCS <BLPRO> to be described
later. This status of the automatic programming operation to set protection bits can be checked by
monitoring FCFLCS <RDY/BSY> . Any new command sequence is not accepted while automatic
programming is in progress to program the protection bits. If it is desired to stop the programming
operation, use the hardware reset function. In this case, it is necessary to perform the programming
operation again because the protection bits may not have been correctly programmed. If all the protection
bits have been programmed, all FCFLCS <BLPRO> are set to "1" indicating that it is in the protected
state. This disables subsequent writing and erasing of all blocks.
pending on the status of the protection bits and the security bits. It depends on the status of FCFLCS
<BLPRO> whether all <BLPRO> are set to "1" or not if FCSECBIT<FCSECBIT> is 0x1. Be sure to
check the value of FCFLCS <BLPRO> before executing the automatic protection bit erase command.
See the chapter "ROM protection" for details.
The automatic block erase operation starts when the sixth bus write cycle of the command cycle is
This status of the automatic block erase operation can be checked by monitoring FCFLCS <RDY/
Also, any protected blocks cannot be erased. If an automatic block erase operation has failed, the
This device is implemented with protection bits. This protection can be set for each block. See Table
Different results will be obtained when the automatic protection bit erase command is executed de-
Note:Software reset is ineffective in the seventh bus write cycle of the automatic protection bit
Note:The TMPM333FYFG is configured with block 2 through 5. Block 0 and 1 require a pro-
Automatic block erase (for each block)
Automatic programming of protection bits (for each block)
Automatic erasing of protection bits
・ When all the FCFLCS <BLPRO> are set to "1" (all the protection bits are programmed):
programming command. FCFLCS <RDY/BSY> turns to "0" after entering the seventh bus
write cycle.
gramming of protection bits when using security function.
is automatically initialized within the device. When the seventh bus write cycle is comple-
ted,the entire area of the flash memory data cells is erased and then the protection bits are
erased. This operation can be checked by monitoring FCFLCS <RDY/BSY>. If the automatic
operation to erase protection bits is normally terminated, FCFLCS will be set to
"0x00000001".While no automatic verify operation is performed internally to the device, be
sure to read the data to confirm that it has been correctly erased. For returning to the read mode
while the automatic operation after the seventh bus cycle is in progress, it is necessary to use
the hardware reset to reset the device. If this is done, it is necessary to check the status of
When the automatic protection bit erase command is command written, the flash memory
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TMPM333FDFG/FYFG/FWFG