TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 455

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

17.6.3.2
OUTPUT DATA
INPUT DATA
SCK Clock High width (input)
SCK Clock Low width (input)
SCK cycle
Output Data ← SCK rise
SCK rise → Output Data hold
Valid Data input ← SCK rise
SCK rise → Input Data hold
SCK cycle (programmable)
Output Data ← SCK rise
SCK rise → Output Data hold
Valid Data input ← SCK rise
SCK rise → Input Data hold
cycle time. It varies depending on the programming of the clock gear function.
(1)
(2)
In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys
Clock-Synchronous 8-Bit SIO mode
SCK
SO
SI
50% duty cycle.)
50% duty cycle.)
Note:Keep this value positive by adjusting SCK cycle.
SCK Input Mode (The electrical specifications below are for an SCK signal with a
SCK Output Mode (The electrical specifications below are for an SCK signal with a
Parameter
Parameter
t
t
SRD
OSS
Symbol
Symbol
VALID
t
t
t
t
t
t
t
t
t
t
t
0
t
t
0
SCH
SCY
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
SCL
SCY
Page 435
t
SCY
t
t
t
SCH
t
SCY
SCY
SCY
/2 − 3x − 45
30 − x
Min
Min
16x
/2 − 20
/2 − 20
4x
4x
30
45
+ t
/2 + x
0
VALID
Equation
Equation
SCL
1
1
t
SCH
t
HSR
t
OHS
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
t
SCL
VALID
2
(Note)
2
100
100
200
−20
125
400
180
180
Min
Min
30
45
5
0
40 MHz
40 MHz
TMPM333FDFG/FYFG/FWFG
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
VALID
3
3
Unit
Unit
ns
ns