TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 379

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

14.4
14.4.1
14.4.2
The RTC incorporates a second counter that generates a 1Hz signal from a 32.768 kHz signal.
The second counter operation must be taken into account when using the RTC.
Operational Description
A carry during writing ruins correct data writing. The following procedure ensures the correct data writing.
Reading clock data
Writing clock data
1. Using 1Hz interrupt
2. Using pair reading
1. Using 1 Hz interrupt
2. Resetting counter
during reading. To ensure correct data reading, read the clock data twice as shown below. A pair of
data read successively needs to match.
is written in the time between 1Hz interrupt and subsequent one second count, it completes correctly.
The 1Hz interrupt is generated being synchronized with counting up of the second counter.
Data can be read correctly if reading data after 1Hz interrupt occurred.
There is a possibility that the clock data may be read incorrectly if the internal counter operates carry
The 1Hz interrupt is generated by being synchronized with counting up of the second counter. If data
Write data after resetting the second counter.
The 1Hz-interrupt is generated one second after enabling the interrupt subsequent to counter reset.
The time must be set within one second after the interrupt.
Figure 14-2 Flowchart of the clock data reading
RTCPAGER<PAGE> = "0",
then select PAGE0
Clock data reading
Clock data reading
1st data = 2nd data
(2nd)
Start
(1st)
End
Page 359
YES
NO
TMPM333FDFG/FYFG/FWFG