TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 380

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

14.4
Operational Description
3. Disabling the clock
Writing "0" to RTCPAGER<ENATMR> disables clock operation including a carry.
Stop the clock after the 1Hz-interrupt. The second counter keeps counting.
Set the clock again and enable the clock within one second before next 1Hz-interrupt
Figure 14-3 Flowchart of the clock data writing
Figure 14-4 Flowchart of the disabling clock
RTCRESTR<RSTTMR> = "1" then
RTCRESTR<DIS1HZ> = "0" then
RTCPAGER<PAGE> = "0" then
enable 1Hz interrupt
Writing the clock data
select PAGE0
reset counter
Timer setting
Enabling the clock
First interrupt
Disabling clock
(After 1s)
Page 360
Strat
End
Start
End
YES
NO
TMPM333FDFG/FYFG/FWFG