TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 454

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

17.6
AC Electrical Characteristics
17.6.3
17.6.3.1
SCL clock frequency
Hold time for START condition
SCL Low width (Input) (Note 1)
SCL High width (Input) (Note 2)
Setup time for a repeated START condition
Data hold time (Input) (Note 3, 4)
Data setup time
Setup time for a STOP condition
Bus free time between stop condition and
start condition
Note 1: SCL clock Low width (output) = (2
Note 2: SCL clock High width (output) = (2
Note 3: The output data hold time is equal to 12x of internal SCL.
Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for
Note 5: Software -dependent
Note 6: The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is switched off, the
SCL
SDA
Serial Bus Interface(I2C/SIO)
cycle time. It varies depending on the programming of the clock gear function.
100kHz, Fast mode is 400khz. Internal SCL Frequency setting should comply with Note1 & Note2 shown above.
the SDA signal to bridge the undefined region of the falling edge of SCL. However, this SBI does not satisfy this
requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore,
the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, in-
cluding tr/tf of the SCL and SDA lines.
SDA and SCL I/O pins must be floating so that they don't obstruct the bus lines. However, this SBI does not
satisfy this requirement.
In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys
n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBIxCR.
I2C Mode
Parameter
Sr: Repeated start condition
S: Start condition
P: Stop condition
t
HD;STA
S
t
f
t
LOW
t
SU;DAT
t
SCL
t
r
t
t
Symbol
t
t
t
HD; STA
SU; STA
HD; DAT
SU; DAT
SU; STO
t
t
t
t
HIGH
t
LOW
SCL
BUF
HIGH
n - 1
n - 1
+ 58)/x
+ 12)/x On I2C-bus specification, Maximum Speed of Standard Mode is
(Note5)
(Note5)
t
HD;DAT
Min
−
−
−
−
−
−
0
Page 434
Equation
Max
−
−
−
−
−
−
−
−
−
Standard Mode
Min
250
4.0
4.7
4.0
4.7
0.0
4.0
4.7
0
t
Sr
SU;STA
Max
100
−
−
−
−
−
−
−
−
TMPM333FDFG/FYFG/FWFG
t
SU;STO
100
Min
0.6
1.3
0.6
0.6
0.0
0.6
1.3
0
Fast Mode
P
t
Max
BUF
400
−
−
−
−
−
−
−
−
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs